The present disclosure relates to a test circuit including a device under test which is used for performance evaluation at a wafer level in the middle of manufacture of a semiconductor device, for example, and a layout method for the test circuit, and an integrated circuit fabricated by using a same layout method as the layout method for the test circuit.
In related art, a test structure for wafer shipment inspection, which is referred to as a TEG (Test Element Group), is provided on a wafer (substrate) to perform electrical performance evaluation at a wafer level in the middle of a process of manufacturing a semiconductor device. The test structure generally includes a plurality of devices under test (hereinafter referred to as DUTs), an electrode pad to be brought into contact with a probe of an evaluating device such as a wafer tester, for example, and connecting wiring (connecting pin) for establishing electric connection between the DUTs and the electrode pad.
In addition, in related art, various layout design patterns in such a test structure have been proposed (see U.S. Pat. No. 7,489,151, referred to as Patent Document 1 hereinafter, for example). FIG. 21 shows a schematic configuration of a layout design pattern of a test structure proposed in Patent Document 1. Incidentally, FIG. 21 is a schematic plan view of one DUT and the vicinity of the DUT.
Patent Document 1 describes an example using a MOS (Metal-Oxide-Semiconductor) transistor 200 as a DUT. According to Patent Document 1, as shown in FIG. 21, a connecting pin formed by an L-shaped routing structure 201 is connected to each of a gate, a drain, a source, and a well (body) of the MOS transistor 200.